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INTEGRATED CIRCUITS
DATA SHEET
TDA8783 40 Msps, 10-bit analog-to-digital interface for CCD cameras
Product specification Supersedes data of 1998 Jul 31 File under Integrated Circuits, IC02 1999 Jun 25
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
FEATURES * Correlated Double Sampling (CDS), AGC, 10-bit ADC and reference regulator included, adjustable bandwidth (CDS and AGC) * Fully programmable via a 3-wire serial interface * Sampling frequency up to 40 MHz * AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps) * CDS programmable bandwidth from 4 to 120 MHz * AGC programmable bandwidth from 4 to 54 MHz * Standby mode available for each block for power saving applications 20 mW (typ.) * 6 dB fixed gain analog output for analog iris control * 8-bit and 10-bit DAC included for analog settings * Low power consumption of only 483 mW (typ.) * 5 V operation and 2.5 to 5.25 V operation for the digital outputs * TTL compatible inputs, TTL and CMOS compatible outputs. ORDERING INFORMATION TYPE NUMBER TDA8783HL PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm APPLICATIONS * CCD camera systems. GENERAL DESCRIPTION
TDA8783
The TDA8783 is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC and a low-power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator. The AGC and CDS have a bandwidth circuit controlled by on-chip DACs via a serial interface. A 10-bit DAC controls the ADC input clamp level. An additional 8-bit DAC is provided for additional system controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT.
VERSION SOT313-2
1999 Jun 25
2
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ADCres Vi(CDS)(p-p) GCDS fCLK(max) AGCdyn Ntot(rms) PARAMETER analog supply voltage digital supply voltage digital outputs supply voltage analog supply current digital supply current digital outputs supply current ADC resolution CDS input voltage (peak-to-peak value) CDS output amplifier gain maximum clock frequency AGC dynamic range total noise from CDS input to ADC output (RMS value) total power consumption gain = 4.5 dB; fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz fCLK = 27 MHz; CL = 20 pF; ramp input CONDITIONS MIN. 4.75 4.75 2.5 - - - - - - 40 - - TYP. 5 5 3 78 18 1 10 400 6 - 30 0.125
TDA8783
MAX. 5.25 5.25 5.25 85 20 - - 1200 - - - -
UNIT V V V mA mA mA bits mV dB MHz dB LSB
Ptot
-
483
550
mW
1999 Jun 25
3
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
BLOCK DIAGRAM
TDA8783
handbook, full pagewidth IND
INP AGND3 VCCA3 SHD 46 48 45 44
SHP 43
CLPOB CLPDM 1 42
CLK 41
DGND2 40
VCCD2 39
OE 38
VCCO 37
47
36 TRACKAND-HOLD TRACKAND-HOLD CLOCK GENERATOR 35
OGND
TRACKAND-HOLD 8 5 4-BIT DAC CUT-OFF CLAMP ref1
D9
34 CLAMP 33
CPCDS AGND1
D8
D7
32
D6
31 AMPOUT AGND4 4 2 6 dB 10-BIT ADC OUTPUTS BUFFER
D5
30
TDA8783
7 1 AGC 29
D4
AGCOUT
D3
28 VCCA1 AGND5 ADCIN 6 9 10 1 4-BIT DAC CUT-OFF 9-BIT DAC
D2
27
D1
26 25 + 8-BIT DAC 10-BIT DAC REGULATOR SERIAL INTERFACE 3
D0 DGND1 OFDOUT
Vref CLPADC
12 11
13 DACOUT
14
15
16
17
18
19
23
22 SEN
21
20
24 VCCD1
MGM491
VCCA2 VRB
VRT
AGND6 DEC1 STDBY
SDATA SCLK
AGND2
Fig.1 Block diagram.
1999 Jun 25
4
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
PINNING SYMBOL CLPOB AGND4 OFDOUT AMPOUT AGND1 VCCA1 AGCOUT CPCDS AGND5 ADCIN CLPADC Vref DACOUT AGND2 VCCA2 VRB VRT DEC1 AGND6 SDATA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clamp pulse input at optical black analog ground 4 DESCRIPTION
TDA8783
analog output of the additional 8-bit control DAC (controlled via the serial interface) CDS amplifier output (fixed gain = 6 dB) analog ground 1 analog supply voltage 1 AGC amplifier signal output clamp storage capacitor pin analog ground 5 ADC analog signal input from AGCOUT via a short circuit clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground) ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or shorted to ground via a capacitor) DAC output for ADC clamp level analog ground 2 analog supply voltage 2 ADC reference voltage (BOTTOM) code 0 ADC reference voltage (TOP) code 1023 decoupling 1 (decoupled to ground via a capacitor) analog ground 6 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off, additional 8-bit DAC for OFD output voltage and 10-bit DAC for ADC clamp level and standby mode per block and edge pulse control; see Table 1 serial clock input for the control DACs and their serial interface; see Table 1 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1 standby control (active HIGH); all the output bits are logic 0 when standby is enabled digital supply voltage 1 digital ground 1 ADC digital output 0 (LSB) ADC digital output 1 ADC digital output 2 ADC digital output 3 ADC digital output 4 ADC digital output 5 ADC digital output 6 ADC digital output 7 ADC digital output 8 ADC digital output 9 (MSB) digital output ground digital output supply voltage
SCLK SEN STDBY VCCD1 DGND1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OGND VCCO
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
1999 Jun 25
5
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
SYMBOL OE VCCD2 DGND2 CLK CLPDM SHP SHD VCCA3 INP IND AGND3 PIN 38 39 40 41 42 43 44 45 46 47 48 digital supply voltage 2 digital ground 2 ADC clock input clamp pulse input at dummy pixel pre-set sample-and-hold pulse input data sample-and-hold pulse input analog supply voltage 3 pre-set input signal from CCD data input signal from CCD analog ground 3 DESCRIPTION
TDA8783
output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance)
40 DGND2
42 CLPDM
48 AGND3
39 VCCD2
45 VCCA3
37 VCCO
44 SHD
43 SHP
41 CLK
47 IND
46 INP
38 OE
CLPOB AGND4 OFDOUT AMPOUT AGND1 VCCA1 AGCOUT CPCDS AGND5
1 2 3 4 5 6
36 OGND 35 D9 34 D8 33 D7 32 D6 31 D5
TDA8783H
7 8 9 30 D4 29 D3 28 D2 27 D1 26 D0 25 DGND1
ADCIN 10 CLPADC 11 Vref 12
DACOUT 13
AGND2 14
AGND6 19
VCCD1 24
SCLK 21
VCCA2 15
DEC1 18
SDATA 20
SEN 22
VRB 16
VRT 17
STDBY 23
MGM492
Fig.2 Pin configuration.
1999 Jun 25
6
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage difference between VCCA and VCCD between VCCA and VCCO between VCCD and VCCO Vi VCLK(p-p) Io Tstg Tamb Tj Note input voltage AC input voltage for switching (peak-to-peak value) output current storage temperature operating ambient temperature junction temperature referenced to AGND referenced to DGND -1.0 -1.0 -1.0 -0.3 - - -55 -20 - +1.0 +4.0 +4.0 +7.0 CONDITIONS note 1 note 1 note 1 MIN. -0.3 -0.3 -0.3
TDA8783
MAX. +7.0 +7.0 +7.0 V V V V V V V V
UNIT
VCCD 10 +150 +75 150
mA C C C
1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 and +7.0 V provided that the supply voltage difference VCC remains as indicated. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 76 UNIT K/W
thermal resistance from junction to ambient in free air
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
CHARACTERISTICS VCCA = VCCD = 5 V; VCCO = 3 V; fCLK = 27 MHz; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO Digital inputs CLOCK INPUT: CLK (REFERENCED TO DGND) VIL VIH IIL IIH Zi Ci VIL VIH IIL IIH VIL VIH Ii Vi(CDS)(p-p) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance VCLK = 0.8 V VCLK = 2.0 V fCLK = 27 MHz fCLK = 27 MHz 0 2.0 -1 - - - 0 2.0 VIL = 0.6 V VIH = 2.2 V - - 0 2.0 -2 - -2 fi(CDS1,2) = fCLK(pix); Vi(CDS)(p-p) = 600 mV black-to-white transition in 1 pixel (1 LSB typ.); fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz 8 - - - - 46 1 - - -6 0 - - - analog supply voltage digital supply voltage digital outputs supply voltage analog supply current digital supply current digital outputs supply current CL = 20 pF on all data outputs; ramp input 4.75 4.75 2.5 - - - 5 5 3 78 18 1 PARAMETER CONDITIONS MIN. TYP.
TDA8783
MAX.
UNIT
5.25 5.25 3.6 85 20 -
V V V mA mA mA
0.8 VCCD +1 20 - - 0.8 VCCD - - 0.8 VCCD +2
V V A A k pF
INPUTS: SHP AND SHD LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current V V A A V V A
INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC LOW-level input voltage HIGH-level input voltage input current
Correlated Double Sampling; CDS CDS input amplitude (peak-to-peak value) CDS control pulses minimum active time 400 - - 1200 +2 - mV A ns
ICPCDS,INP,IND input current pins 8, 46 and 47 tCDS(min)
thd1 thd2
hold time INP compared to control see Fig.5 pulse SHP hold time of IND compared to control pulse SHD see Fig.5
- -
1 1
- -
ns ns
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
SYMBOL tset(CDS) PARAMETER CDS setting time CONDITIONS control DAC 4 bits input code; AGC gain = 0 dB; fcut(AGC) = 54 MHz; Vi(CDS) = 600 mV (p-p) black-to-white transition in 1 pixel (1 LSB typ.) 0000 0001 0010 0011 0100 0111 1000 1011 1111 Amplifier outputs GAMPOUT ZAMPOUT VAMPOUT(p-p) VAMPOUT(bl) VAGCOUT(p-p) VAGCOUT(bl) ZAGCOUT(bl) IAGCOUT GAGC(min) GAGC(max) fcut(AGC) output amplifier gain output amplifier impedance output amplifier dynamic voltage (peak-to-peak value) output amplifier black level voltage AGC output amplifier dynamic voltage level (peak-to-peak value) AGC output amplifier black level voltage AGC output amplifier output impedance AGC output static drive current minimum gain of AGC circuit maximum gain of AGC circuit cut-off frequency AGC Vref connected to DACOUT at 10 kHz static AGC DAC input code = 00 (9-bit control) AGC DAC input code 319 (9-bit control) 4-bit control DAC input code = 00 input code = 15 Clamps gm(ADC) gm(CDS) ADC clamp transconductance CDS clamp transconductance at clamp level at clamp level - - 7 1.5 - - 54 4 - - - - - - - - - - 6 300 2.4 1.5 2000 Vref 5 - 4.5 34.5 - - - - - - - - - 8 21 42 52 82 94 195 219 280 MIN. TYP.
TDA8783
MAX.
UNIT
- - - - - - - - - - - - - - - - 1 - -
ns ns ns ns ns ns ns ns ns
dB V V mV V mA dB dB
- - - -
MHz MHz
mS mS
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - 2 1.5 3.5 - 0.6 0.2 -
TDA8783
MAX. - - - - - - - +120 1.5 0.75 5 -
UNIT
Analog-to-Digital Converter; ADC fCLK(max) tCPH tCPL SRCLK Vi(ADC)(p-p) VRB VRT IADCIN INL DNL td(s) td maximum clock frequency clock pulse width HIGH clock pulse width LOW clock input slew rate (rising and falling edge) ADC input voltage level (peak-to-peak value) ADC reference voltage output code 0 ADC reference voltage output code 1023 ADC input current integral non-linearity differential non-linearity sampling delay time ramp input ramp input 10% to 90% 40 12 12 0.5 - - - -2 - - - 50% at rising edges - CLK and SHD: transition full scale code 0 to 1023; fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz; Vi(CDS) = 600 mV fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz; note 1 GAGC = 4.5 dB GAGC = 34.5 dB Voffset(h-d) maximum offset between CCD heating level and CCD dark pixel level equivalent input noise voltage (RMS value) AGC gain = 34.5 dB AGC gain = 4.5 dB - - -200 0.125 1.6 - - - +200 LSB LSB mV MHz ns ns V/ns V V V A LSB LSB ns
Total chain characteristics (CDS + AGC + ADC) time delay between SHD and CLK 30 ns
No(rms)
output noise (RMS value)
Vn(i)(eq)(rms)
- - -
125 150
- - -
V V
Digital-to-Analog Converters (OFDOUT DAC) VOFDOUT(p-p) additional 8-bit control DAC (OFD) output voltage (peak-to-peak value) DC output voltage for code 0 additional 8-bit control DAC (OFD) output impedance OFD output current drive static 1.4 V
VOFDOUT(0) ZOFDOUT IOFDOUT
- - - -
2.3 3.7 2000 -
- - - 50
V V A
VOFDOUT(255) DC output voltage for code 255
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
SYMBOL PARAMETER CONDITIONS - MIN. TYP.
TDA8783
MAX. -
UNIT
ADC clamp control DAC (see Fig.8) VDACOUT(p-p) ADC clamp 10-bit control DAC output voltage (peak-to-peak value) DC output voltage ADC clamp control DAC output impedance DAC output current drive maximum offset error of DAC + ADC clamp loop static code 0 code 1023 IOH = -1 mA IOL = 1 mA 0 V < Vo < VCCO Ci = 20 pF; VCCO = 5 V Ci = 10 pF Ci = 20 pF; VCCO = 3 V Ci = 10 pF Ci = 20 pF; VCCO = 2.5 V Ci = 10 pF Serial interface fSCLK(max) Notes 1. Noise measurement at ADC outputs: the coupling capacitor at the input is connected to ground, so that only the noise contribution of the front-end is evaluated. The front-end operates at 18 Mpix with a line of 1024 pixels. The first 40 are used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels. The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise is taken into account as no signal is input. 2. Depending on operating pixel frequency, the output voltage and capacitance must be determined according to the output delay timings (to(d)). maximum frequency of serial interface 5 - - MHz code 0 code 1023 ZDACOUT IDACOUT OFELOOP 1 V
VDACOUT
- - - - - -
1.5 2.5 - - 5 5
- - 250 50 - -
V V A LSB LSB
Digital outputs (fCLK = 40 MHz; CL = 20 pF); note 2 VOH VOL IOZ to(h) to(d) HIGH-level output voltage LOW-level output voltage output current in 3-state mode output hold time output delay time VCCO - 0.5 - 0 -20 8 - - - - - - - - - 17 15 20 17 22 18 VCCO 0.5 +20 - 23 21 29 25 33 28 V V A ns ns ns ns ns ns ns
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
handbook, full pagewidth
SDATA D0 SCLK LSB D1 D2 D3
SHIFT REGISTER D4 D5 D6 D7 D8 D9 MSB 10 LATCH SELECTION A0 A1 A2
SEN
8 (D7 to D0) OFD LATCHES
8 (D7 to D0) AGC GAIN LATCHES
8 (D7 to D0) FREQUENCY LATCHES
7 (D6 to D0) PARTIAL STANDBY AND EDGE
10 (D9 to D0) CLAMP REFERENCE LATCHES
8-bit DAC
AGC control
frequency control CDS and AGC
standby control or edge clocks
10-bit DAC
MGM515
Fig.3 Serial interface block diagram.
handbook, full pagewidth
tsu2 MSB thd4 D9 D8 D7 D6 D5 D4 LSB D3 D2 D1 D0
SDATA
A2
A1
A0
SCLK
SEN
MGE373
tsu1
thd3 tsu3
tsu1 = tsu2 = 4 ns (min.); thd3 = thd4 = 4 ns (min.).
Fig.4 Loading sequence of control DACs input data via the serial interface.
1999 Jun 25
12
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
Table 1 Serial interface programming ADDRESS BITS DATA BITS D9 to D0 A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 OFD output control (D7 to D0).
TDA8783
Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0. AGC gain control (D8 to D0). Partial standby controls for power consumption optimization. Only the 4 LSBs (D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and clock ADC: D0 = 1: CDS + AGC in standby; ICCA + ICCD = 48 mA D1 = 1: OFD DAC in standby; ICCA + ICCD = 98 mA D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby; ICCA + ICCD = 98.5 mA D3 = 1: SHP and SHD activated with falling edge (for positive pulse) D4 = 1: CLPDM, CLPOB and CLPADC activated on high level; note 1 D5 = 0: CLKADC activated with falling edge D6 must be set to logic 0.
1 Note
0
0
Clamp reference DAC (D9 to D0).
1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level Vref. Vref is connected to ground via a capacitor. Table 2 Standby selection STDBY 1 0 DATA BITS D9 to D0 LOW active ICCA + ICCD (TYP.) 4 mA 99 mA
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
handbook, full pagewidth
INP and IND
N
N+1
N+2
N+3
SHP
1.4 V
tCDS thd1
SHD
1.4 V
thd2 CLK
td tCPH 1.4 V
td(s) ADC
N
to(d)
to(h) 90% DATA 10% N-1 N
MGR395
Fig.5 Pixel frequency timing diagram.
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
handbook, full pagewidth
1 pixel
1 pixel
AGCOUT
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBLACK
DUMMY
VIDEO
CLPDM2 CLPADC WINDOW CLPOB (active HIGH) CLPDB WINDOW CLPDM (active HIGH)
(1)
CLPDMR CLPADC WINDOW
CLPADC (active HIGH)
(1)
MGR396
(1) When dummy pixels are not available.
Fig.6 Line frequency timing diagram.
1999 Jun 25
15
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
handbook, halfpage
MGM507
34.5 GAGC (dB)
4.5
0
319 AGC control DAC input code
511
Fig.7 AGC gain as a function of DAC input code.
handbook, full pagewidth
MGM508
2.5 ADC CLAMP DAC voltage output (V)
3.4 OFD DAC voltage output (V)
1.5 0
2.0 1023 ADC CLAMP control DAC input code 0 255 OFD control DAC input code
Fig.8 DAC voltage output as a function of DAC input code.
1999 Jun 25
16
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
I handbook, halfpage (A) +100
0 2.85 -100 200 mV
MGR397
V (V)
Fig.9 Typical clamp current for pin CPCDS.
I handbook, halfpage (A) +300
0 2.85 -300 400 mV
MGR398
V (V)
Fig.10 Typical clamp current for pins IND and INP.
I handbook, halfpage (A) +200
0 Vref -200 400 mV
MGR399
V (V)
Fig.11 Typical clamp current for pin Vref.
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
handbook, full pagewidth
160
MGR441
fcut (MHz) 120
(2) (3) (4)
300 tset (ns) 250
200
80
(1)
150
100 40 50
0
0
1
2
3
4
5
6
7
8
9
A
B
C D E 4-bit control DAC input code
F
0
(1) fcut. (2) tset (10 bits accuracy). (3) tset (9 bits accuracy). (4) tset (8 bits accuracy).
Fig.12 CDS setting time and bandwidth.
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
handbook, full pagewidth
60
MGR401
fcut (MHz)
40
20
0 0 1 2 3 4 5 6 7 8 9 A B C D E 4-bit control DAC input code F
Fig.13 AGC bandwidth.
handbook, full pagewidth
(1)
1.6
MGR442
Vo(CDS)(p-p) (V) 1.2
(2)
(3) (4) (5)
0.8
(6)
0.4
0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vi(CDS)(p-p) (V) 1.6
(1) tset(CDS) = 12 ns (2) tset(CDS) = 10 ns
(3) tset(CDS) = 8 ns (4) tset(CDS) = 7 ns
(5) tset(CDS) = 6 ns (6) tset(CDS) = 5 ns
Fig.14 CDS output.
1999 Jun 25
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Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
TDA8783
handbook, full pagewidth
3
MGR443
Ntot(rms) (LSB)
(1)
2
(2) (3)
(4)
1
(5) (6)
0 00 (4.5) 40 (10.5) 80 (16.5) C0 (22.5) 100 (28.5) code GAGC (dB) 13F (34.5)
(1) (2) (3) (4)
fpix = 27 MHz; control DAC = 00H; fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz. fpix = 18 MHz; control DAC = 10H; fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz. fpix = 10 MHz; control DAC = 31H; fcut(CDS) = 80 MHz; fcut(AGC) = 30 MHz. fpix = 5 MHz; control DAC = 43H; fcut(CDS) = 35 MHz; fcut(AGC) = 12 MHz. (5) fpix = 1 MHz; control DAC = F8H; fcut(CDS) = 6 MHz; fcut(AGC) = 4 MHz. (6) fpix = 375 kHz; control DAC = FFH; fcut(CDS) = 4 MHz; fcut(AGC) = 4 MHz.
Fig.15 Output noise (RMS value).
1999 Jun 25
20
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
APPLICATION INFORMATION
TDA8783
handbook, full pagewidth
CCD
5.0 V
5.0 V
2.5 to 5.25 V
(3)
(3)
(3)
220 nF
from timing generator
AGND3
CLPDM
DGND2
VCCD2
VCCA3
SHD
SHP
IND
INP
48 47 46 45 44 43 42 41 40 39 38 37 CLPOB AGND4 OFDOUT AMPOUT AGND1
(3)
VCCO
CLK
OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DACOUT VCCA2 SDATA SCLK AGND6 STDBY VRB SEN AGND2 VCCD1 VRT DEC1
36 35 34 33 32 31
OGND D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1
5.0 V 1 F
VCCA1 AGCOUT CPSDS AGND5 ADCIN
TDA8783
30 29 28 27 26 25
1 F
CLPADC Vref
(2)
(1)
100 nF 5.0 V
(3)
2.2 nF 1 nF 1 nF
serial interface
(3)
5.0 V
MGM504
Depending on the application, the following connections must be made: (1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface (clamp ADC activated). (2) Clamp ADC not activated, direct connection from DACOUT to Vref. (3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.
Fig.16 Application diagram.
1999 Jun 25
21
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
Power and grounding recommendations When designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras, care should be taken to minimize the noise. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analogue components (such as classical operational amplifiers) must be respected, particularly with respect to power and ground connections. The following additional recommendation is given for the CDS input pin(s) which is/are internally connected to the programmable gain amplifier: * The connections between CCD interface and CDS input should be as short as possible and a ground ring protection around these connections can be beneficial. Separate analogue and digital supplies provide the best solution. If it is not possible to do this on the board then the analogue supply pins must be decoupled effectively from the digital supply pins. If the same power supply and ground are used for all the pins then the decoupling capacitors must be placed as close as possible to the IC package.
TDA8783
* In a two-ground system, in order to minimize the noise though package and die parasitics, the following recommendations must be implemented: - All the analogue and digital supply pins must be decoupled to the analogue ground plane. Only the ground pin associated with the digital outputs must be connected to the digital ground plane. All the other ground pins should be connected to the analogue ground plane. The analogue and digital ground planes must be connected together at one point as close as possible to the ground pin associated with the digital outputs. - The digital output pins and their associated lines should be shielded by the digital ground plane which can be used then as return path for digital signals.
1999 Jun 25
22
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
TDA8783
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
ISSUE DATE 94-12-19 97-08-01
1999 Jun 25
23
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA8783
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Jun 25
24
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable
TDA8783
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Jun 25
25
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
NOTES
TDA8783
1999 Jun 25
26
Philips Semiconductors
Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras
NOTES
TDA8783
1999 Jun 25
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 66
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/25/02/pp28
Date of release: 1999 Jun 25
Document order number:
9397 750 06031

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